2025-07
2025-07-31
FT601 FIFO
FT601 FIFO Migen Implementation
What are the limitations of increasing the frequency beyond 1Hz for PPS signals
The limitations of increasing the frequency beyond 1 Hz for PPS signals primarily relate to signal shape, timing accuracy, propagation effects, hardware complexity, and pulse distortion:
- Pulse shape and duty cycle ambiguity: PPS signals at 1 Hz are usually short pulses with sharply defined edges to precisely mark second boundaries. Increasing frequency means pulse widths and separation shrink, possibly turning the signal into something closer to a square wave or continuous periodic waveform, which can blur the definition of distinct timing edges important for synchronization^1.
- Increased pulse distortion and rise time issues: Higher frequency pulses have faster rise times and shorter durations, making them more susceptible to distortions when transmitted over cables. Dispersion, attenuation, impedance mismatches, and cable length affect the pulse shape and timing delay more severely at higher frequencies, thus degrading timing precision^4.
- Measurement and detection uncertainty: Timing devices rely on clear, stable pulse edges to trigger time measurements. Faster pulses from higher frequency signals increase uncertainties in detection due to limited bandwidth, noise, and trigger thresholds, worsening jitter and reducing synchronization quality^4.
- Hardware and distribution challenges: Generating and distributing high-frequency pulses with ultra-low jitter and minimal distortion over long distances requires expensive, specialized hardware and careful design. 1 Hz PPS signals are simpler and more robust for typical synchronization scenarios^2.
- Loss of well-defined absolute timing boundaries: The main advantage of 1 Hz PPS is that each pulse corresponds to an exact whole second boundary, facilitating phase alignment of clocks. At higher frequencies, while more timing points may be generated, the direct correlation with absolute second boundaries becomes less clear, complicating protocols that rely on these markers.
In essence, increasing frequency beyond 1 Hz for PPS-type signals tends to increase system complexity, degrade pulse integrity and timing accuracy, and reduce the clarity of the timing reference that makes 1 PPS signals highly effective for synchronization applications such as GPS timing, network clocks, and telecom networks^1.
If needed, systems requiring finer resolution within each second typically use a combination of stable local high-frequency clocks disciplined by the 1 Hz PPS signal rather than replacing PPS with higher frequency pulses directly^2.
Renesas FPGA
Shrike is world's first fully open source FPGA Dev board based on Renesas Forge FPGA SLG47910 and RP2040.
2025-07-30
Numato FPGA Boards have FT2232 FIFO Mode
- Styx Z7 (239USD)
- Mimas A7 (229USD)
- Narvi S7 (199USD)
- Mimas A7 Mini (148USD)
- Mimas S7 Lite (99USD)
- Mimas ECP5 Mini (149USD)
Config FT2232H use FT_Prog
How to Config FT2232 to FIFO Mode
2025-07-29
What is Harp
2025-07-28
Thousand Brains Project
Thousand Brains Project Github
Thousand Brains Project Documentation
HARP
Harp Synchronization Clock Protocol
2025-07-25
FT245 Papers
Spartan 6/7 + FT2232 Fifo
Saturn – S6 FPGA Development Board with DDR SDRAM
Data flow Computer
2025-07-24
FT2232 FIFO
HIGHLY ACCURATE PPS CLOCK SYNCHRONIZATION
HIGHLY ACCURATE PPS CLOCK SYNCHRONIZATION
Do this: your measurement of the external reference PPS is driven by a vcxo or even ovcxo. Count the cycles between two rising edges. This will give you your period error. Generate an internal PPS with the same clock and count clock cycles between them. This will give you your phase error. What is left to do is to create a way to control the vcxo either by using a DAC or even PWM. One thing to point out: while technically you have a second to correct the vcxo, the faster you do it,the less error you will have on the next second.
Also, a hint: to speed up the sync, you can do a hard resync, meaning once you have the minimum of the period error, start the internal PPS on the next external PPS. That way, you should also have the minimum of phase error.
The higher the internal sampling frequency, the better your sync will be.
2025-07-23
Async C Lib
Like protothread
Complexity
Complexity a Guide tour, author
2025-07-21
OE Harp Soultions
Harp Timestamp Generator (for Acquisition Board)
SyncBox Pin Assigment
2025-07-15
Lab Stream Layer
LSL is an open-source networked middleware ecosystem to stream, receive, synchronize, and record neural, physiological, and behavioral data streams acquired from diverse sensor hardware.
It reduces complexity and barriers to entry for researchers, sensor manufacturers, and users through a simple, interoperable, standardized API to connect data consumers to data producers while abstracting obstacles such as platform differences, stream discovery, synchronization and fault-tolerance.
https://labstreaminglayer.org/#/
Lora Device T-Deck and Meshastic
2025-07-14
netdevsim，Netwoking Device Simulator for PTP Simulation
netdevsim，Netwoking Device Simulator，网络设备模拟器
Camera Storage for 24/7
How much storage will I need for 24/7 recording?
The amount of storage needed for continuous 24/7 webcam recording
depends on several factors such as video resolution,
frame rate, duration and the video compression algorithm used.
Here are estimated storage requirements as a general guide:
480p at 30fps with medium compression: Approximately 2GB per hour
720p at 30fps with medium compression: Approximately 4GB per hour
1080p at 30fps with medium compression: Approximately 8GB per hour
So for continuous 24/7 recording, you would need about
480p: 54GB per day
720p: 96GB per day
1080p: 192GB per day
Camera MTBF
If you have four cameras with an individual MTBF of 1000 hours,
and they are used concurrently, the overall system MTBF will also be 1000 hours,
assuming the cameras fail independently.
The number of cameras doesn't directly affect the system MTBF.
USB Camera with Multi Framebuffer
2025-07-10
Pi for
-
Instrumentation
- UART
- IO Port
- USB (Other Instrument)
- PCIe (pi5)
-
MCU Programming
- Arduino
- MicroPython-Thonny
- PICO SDK
-
Linux Programming
- C/C++
- golang
- Python
2025-07-09
2025-07-07
Phy Support IEEE1588
RTL8211FS(I)-VS-CG
- Complete hardware support for Synchronous Ethernet and Precision Time Protocol (PTP) including - - IEEE 1588v1, v2, and 802.1AS (RTL8211FS(I)-VS-CG only)
- PTP Packet parser supports Layer 2 Ethernet, IPv4/UDP, IPv6/UDP packets (RTL8211FS(I)-VS-CG only)
- PTP One-Step operation supported (RTL8211FS(I)-VS-CG only)
- PTP clock synchronization (RTL8211FS(I)-VS-CG only)
- PTP timestamp with 8ns resolution (RTL8211FS(I)-VS-CG only)
- Deterministic and low transmission latency for PTP mechanism (RTL8211FS(I)-VS-CG only)
- Adjustable PTP clock (RTL8211FS(I)-VS-CG only)
- Two PTP GPIOs as programmable Time Application Interfaces (RTL8211FS(I)-VS-CG only)
- Low-jitter synchronized PTP clock output (RTL8211FS(I)-VS-CG only)
- Selectable PTP clock input from the external reference clock source (RTL8211FS(I)-VS-CG only)
The BRAIN Initiative archive for publishing and sharing neurophysiology data including electrophysiology, optophysiology, and behavioral time-series, and images from immunostaining experiments
MDIO/MDC
SMI：串行管理接口（Serial Management Interface），通常直接被稱為MDIO接口（Management Data Input/
Output Interface）。MDIO最早在IEEE 802.3的第22卷定義，後來在第45卷又定義了增強版本的MDIO，其主要被應用於以
太網的MAC和PHY層之間，用於MAC層器件通過讀寫寄存器來實現對PHY層器件的操作與管理。
MDIO主機（即產生MDC時鐘的設備）通常被稱為STA（Station Management Entity），而MDIO從機通常被稱為MMD
（MDIO Management Device）。通常STA都是MAC層器件的一部分，而MMD則是PHY層器件的一部分。MDIO接口包括兩條線，
MDIO和MDC，其中MDIO是雙向數據線，而MDC是由STA驅動的時鐘線。MDC時鐘的最高速率一般為2.5MHz，MDC也可以是非固定
頻率，甚至可以是非週期的。MDIO接口只是會在MDC時鐘的上升沿進行採樣，而並不在意MDC時鐘的頻率（類似於I2C接口）。如
下圖所示。
PHC : PTP Hardware Clock
USB -> Effinix FPGA -> DP83640
Tic-Nic -- A PTP-Capable USB Ethernet Adapter with Hardware I/O
2025-07-04
Pico-Ice
Video Process with FPGA
基因上位作用(epistasis)介紹與發現
computational cognitive neuroscience
computational-cognitive-neuroscience
STM32 -> Ice40
2025-07-03
Makefile for Piython
STM32 WS2812 LED use DMA and PWM
2025-07-02
XILINX TSN
TI Phy Chip for gPTP ,TSN
SOC to MAC Interface MII
Professor Edmund T. Rolls Computational neuroscience theories of brain function and behaviour
Computational neuroscience theories of brain function and behaviour
2025-07-01
WE CE RE 三電極
- WE : Working Electrode
- CE : Counter Electrode
- RE : Reference Electrode
5V to +-5V
