2026-01
2026-01-30 🌐 🎬 💾 📚 📑 🔬🦠🧪
Modified Frame-projected Independent Fiber Photometry (FIP) System_Hardware V.2
🔬🦠🧪Modified Frame-projected Independent Fiber Photometry (FIP) System_Hardware V.2
💾Fiber Photometry System Configuration
sCMOS (scientific Complementary Metal–Oxide–Semiconductor) are a type of CMOS image sensor (CIS).These sensors are commonly used as components in specific observational scientific instruments, such as microscopes and telescopes. sCMOS image sensors offer extremely low noise, rapid frame rates, wide dynamic range, high quantum efficiency, high resolution, and a large field of view simultaneously in one image.
The temporal multiplexing sequence:
Blue LED (470nm) excitation -> Green CMOS camera captures signal from GFP-based sensors UV LED (415nm) excitation -> Green CMOS camera captures isosbestic signal Yellow LED (560nm) excitation -> Red CMOS camera captures signal from RFP-based sensors This cycling occurs at 60 Hz, allowing near-simultaneous measurement of multiple signals while preventing crosstalk between channels. Each LED is activated in sequence and cameras are synchronized to capture data only during their respective LED's ON period.
Protocols.io Bring structure to your research
🔬🦠🧪Protocols.IO
How to Create a Xilinx Board File
🌐Creating Xilinx Vivado board files for EBAZ4205
Petalinux from trenz-electronic
📚Petalinux from trenz-electronic
Petalinux RealTime
🌐MicroZed Chronicles: PREEMPT_RT PetaLinux
🌐Real Time Optimization in Petalinux with RT Patch on MPSoC
Allen Institute for Neural Dynamics
🌐Allen Institute for Neural Dynamics
Neuropixels Electrophysiology platform of Allen Institute
🌐Neuropixels Electrophysiology
Reproducibility is a significant challenge in neuroscience, as analysis and visualization methods are often difficult to replicate due to a lack of accessible code, separation of code from published figures, or unavailability of code altogether. This issue may arise from the complex nature of neuroscience research, the use of diverse data formats and analysis techniques, and insufficient emphasis on open-source, collaborative practices. In addition, key neuroscience analyses are typically rewritten at the start of new scientific projects, slowing down the initiation of research efforts.
PCIe Deep Dive
🌐PCIe Deep Dive, Part 1: Tool Hunt
🌐PCIe Deep Dive, Part 2: Stack and Efficiency
🌐PCIe Deep Dive, Part 3: Scramblers, CRCs, and the Parallel LFSR
🌐PCIe Deep Dive, Part 4: LTSSM
🌐PCIe Deep Dive, Part 5: Flow Control
PCI Express Primer
🌐PCI Express Primer #1 Simon Southwell
🌐PCI Express Primer #2 Simon Southwell
🌐PCI Express Primer #3 Simon Southwell
🌐PCI Express Primer #4 Simon Southwell
Ariel OS
Ariel OS is an operating system for secure, memory-safe, networked applications running on low-power microcontrollers. It is based on Rust from the ground up and supports hardware based on 32-bit microcontroller architectures (Cortex-M, RISC-V, and Xtensa). Many features provided by Ariel OS can individually be enabled or disabled at build time in order to minimize resource consumption.
Zynq Bare-Metal and SSD
🌐Zynq Ultrascale+ FatFs and Direct Speed Tests with Bare Metal NVMe via AXI-PCIe Bridge
🌐Zynq Ultrascale+ Bare Metal NVMe: 2GB/s with FatFs + exFAT
💾FatFs driver for NVME SSD on MicroBlaze
Advanced Real-Time Infrastructure for Quantum physics
ARTIQ features a high-level programming language, based on Python, that helps describing complex experiments. It is compiled and executed on dedicated FPGA hardware with nanosecond timing resolution and sub-microsecond latency.
The time-critical code (a kernel) running on the FPGA (the core device) is easily interfaced with Python code on the computer using a remote procedure call (RPC) mechanism.
MYIR UltraScale Zynq Project
2026-01-29 🌐 🎬 💾 📚 📑
The Task Parallel System Composer (TaPaSCo)
💾The Task Parallel System Composer (TaPaSCo)
Specialized accelerators in a heterogeneous system play a vital role in providing enough compute power for current and upcoming computational tasks. Field-programmable gate arrays (FPGA) are an established platform for such custom and highly specialized accelerators. However, an accelerator implementation alone is only part of the way to a usable system. In order to be used as a specialized co-processor in a heterogeneous setup, the accelerator still needs to be integrated into the overall system and requires a connection to the host (typically a software-programmable CPU) and often also external memory.
AIE, QDMA Streaming and MRMAC
🎬AIE, QDMA Streaming and MRMAC
📚Heterogeneous Accelerated Compute Clusters
使用Buildroot编译AMD/Xilinx Zynq ZC702 单板 Linux （内核和文件系统）
🌐使用Buildroot编译AMD/Xilinx Zynq ZC702 单板 Linux （内核和文件系统）
ZCU104_MPSoC Development - Petalinux 2024.2 Basic Tutorial
🌐ZCU104_MPSoC Development - Petalinux 2024.2 Basic Tutorial
Xillinux
🌐Xillinux: A Linux distribution for Z-Turn Lite, Zedboard, ZyBo and MicroZed
The Xillinux distribution is a software + FPGA code kit for running a full-blown graphical desktop on the Z-Turn Lite, Zedboard and (non-Z7) ZyBo, attaching a monitor, keyboard and mouse to the board itself. Xillinux also supports MicroZed without the graphics.
UltraZed-EG PCIe Carrier Card 開發紀錄
🌐UltraZed-EG PCIe Carrier Card 開發紀錄 使用 PetaLinux 建立系統
Voltage Imaging: all-optical electrophysiology
🎬Adam Cohen, Voltage Imaging: all-optical electrophysiology of neuron excitability
2026-01-28 🌐 🎬 💾 📚 📑
Petalinux Demo
🎬Xilinx Zynq & PetaLinux Project Demo
🎬PetaLinux SPI Device Control LCD Panel
🎬Creating Multi-Boot Bitstream In Xilinx FPGA
🎬Xilinx HLS Project Demo - SHA256 Calculation
HLS Tutorial
Low Latency C++
- cache line aware
- data pre allocation
-
self allocation
-
lock free queue
- no irq
- no time tick irq
-
fix core
-
dma io smart nic
- memory map to io (file)
2026-01-27 🌐 🎬 💾 📚 📑
Time to Digital Converter
DFX over PCIE Bad news for Kintex-UltraScale+ U3 U5 Chip
- XDMA support DFX over PCIE
- QDAM do not
- U11 以上 QDMA Support DFX
Hello FPGA Smart Zynq
FPGA Developer
Ukrain is different from Taiwan in Geo and Wether
🎬Taiwan Is a NIGHTMARE for Drones - My Experience
2026-01-26 🌐 🎬 💾 📚 📑
Low Latency C++ for HFT
Key Approaches for "Interrupt-Free" Linux Behavior:
Key Approaches for "Interrupt-Free" Linux Behavior:
CPU Isolation (isolcpus & IRQ Affinity): Using kernel boot parameters, you can isolate specific CPU cores (isolcpus=) and configure IRQ affinity to force external hardware interrupts to be handled by non-isolated cores.
NOHZ_FULL (Tickless Mode): Enabling nohz_full in the kernel allows a core to stop the periodic timer tick when only one runnable task is present, reducing—but not eliminating—timer interruptions. Asymmetric Multiprocessing (AMP): Running Linux on one core (e.g., CPU0) and a bare-metal application on another (e.g., CPU1). In this setup, CPU1 can run completely without interrupts, while CPU0 handles OS tasks.
Polling (Userspace): Instead of relying on interrupts for peripheral input (e.g., GPIO), specialized user-space applications can poll registers continuously to achieve faster, deterministic, though CPU-intensive, response
Gogole: embedded linux cpu without interrupt
Google: CPU Isolation (isolcpus & IRQ Affinity)
🌐A full task-isolation mode for the kernel
Perfecting PetaLinux Workshop
💾Perfecting PetaLinux Workshop
🎬Perfecting PetaLinux Workshop
📚PetaLinux Tools Documentation: Reference Guide (UG1144)
L_Sort
Vivado Vitis Petalinux 2024 on Ubuntu 2024
🌐Vivado Vitis Petalinux 2024.2
🌐Hardware acceleration in FPGA with Vivado and Vitis
EDA Tools from Europ
Many prominent open source EDA projects such as Coriolis, Edalize, FuseSoC, GHDL, Klayout, Litex, NextPNR, Renode and Yosys are created and developed primarily by Europeans
ossia score
A free, open-source, cross-platform intermedia sequencer for precise and flexible scripting of interactive scenarios. Control and score any OSC-compliant software or hardware: Max/MSP, PureData, openFrameworks, Processing…
2026-01-23 🌐 🎬 💾 📚 📑
Zynq PetaLinux and Vitis
🌐Fixed Platform Design on Zynq-7000 in Vitis 2024.1
Synaptic Self
2026-005
Performance Evaluation of FPGA, GPU, and CPU in FIR Filter Implementation for Semiconductor-Based Systems
Compare device are around 2014.
GPU-Accelerated Audio DSP with PyTorch
TorchFX is a modern Python library for high-performance digital signal processing in audio, leveraging PyTorch and GPU acceleration. Built for researchers, engineers, and developers who need fast, flexible, and differentiable audio processing.
Aptiv GPU Audio is a project implementing three model examples of audio processing VST3 plugins using GPU platform.
Emotion is encode with our memory
Sarah Paine: Greenland, NATO and the Risk of Nuclear War [INTERVIEW]
🎬Sarah Paine: Greenland, NATO and the Risk of Nuclear War [INTERVIEW]
I like her. She is wise.
2026-01-22 🌐 🎬 💾 📚 📑
STM32G4 has over 4 channel DAC
PWM to DC
2026-01-21 🌐 🎬 💾 📚 📑
AD9833 PCB
川普為何需要格林藍
-
打擊 Build a World Wide Cover Missle Launch Base
-
防禦 Build a Radar to watch the Missle from China and Russia
但是無論美洲國如何做 都無法改變 第三次世界大戰的全面毀滅性 中心可能是美洲 因為無論是什麽碗糕穹 都是無效的
Make America Go Away
2026-01-20 🌐 🎬 💾 📚 📑
Analog to Analog
QDMA Concept
ADC Sampling and FFT on Raspberry Pi Pico
MCU APP Lab (Another Maker)
Hope is not a Strategy
美國實業家與圖書收藏家A·愛德華·牛頓曾於1921年這樣寫道[10]
「不論是否飽覽內容，單單是獲得書籍一事，就能使人狂喜，以至於買的書超過了自己的閱讀量——這無異於靈魂的無限延伸……即使沒讀過內容，我們對書籍還是會珍而重之，因為其存在本身就已散發出令人舒適的氣息，並保證我們隨時都能一探內文。」
PCB Return Path
DFX Hardware Interface
MCAP is for PCIE
pyPhotometry on Doric Mini Cube
MicroPython - Build firmware with LVGL and ulab
🎬MicroPython - Build firmware with LVGL and ulab
2026-01-19 🌐 🎬 💾 📚 📑
pMAT (Photometry Modular Analysis Tool)
💾pMAT (Photometry Modular Analysis Tool)
pyPhotometry: Open source Python based hardware and software for fiber photometry data acquisition
📚Fiber Photometry use pyPhotometry
TDT Fiber Photometry System
EMCCD
The Little Book of Stoicism
2026-004
M5Stack Tab5 Demo
Nokia
2026-01-16 🌐 🎬 💾 📚 📑
Zynq SP from Hello FPGA
AMD Learning Center
BCI from Science Corp
🎬The Age of Neural Engineering (ft. Science Corp.)
FT602 Examples
🌐米联客(MSXBO)USB3.0 UVC摄像头基于FT602Q芯片方案
Learning-about-FPGA-DESIGN
Xilinx DFX Tutorial and Resource
🎬Partial Reconfiguration in Vivado on 7 Series
2026-01-15 🌐 🎬 💾 📚 📑
QDMA
Linux QDMA Driver is a kernel mode driver and DPDK PMD is a User Space driver
Remote Direct Memory Access (RDMA) comes into play. RDMA allows direct data transfers between two computers’ memories without involving the CPU, operating system, or most network stack components.
"These queues can be individually configured by interface type, and they function in many different modes", is this the major difference between using queues rather then using channels. As channel can only support 1 PF and can be interfaced with only one among these axi4-mm or axi4-stream and has no modes like in QDMA (internal or bypass mode).
Xilinx DFX Tutorial
🌐 🎬DFX Tutorial
How to Fix USB Blaster
2026-01-14 🌐 🎬 💾 📚 📑
Low Latency Spike Detection
FPGA DFX
📚Dynamic Function eXchange Licensing (UG909)
🎬Dynamic Function Exchange (DFX) (Partial Reconfiguration) with Zynq
🎬AMD Xilinx DFX（Dynamic Function eXchange）テクノロジーの適用事例」【OKI公式】
Usless.
🎬Dynamic partial reconfiguration vivado tutorial 教程
Long but have all the steps.
🎬FPGA102 - FPGA computing systems: Partial Dynamic Reconfiguration
FPGA Tandem
📚UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)
Fiber Photometry Data Pre Processing
Tapered Fiber
My Understanding of Fiber Photometry
Fundamentals of Fiber Photometry: From Theory to Troubleshooting
🎬Fundamentals of Fiber Photometry: From Theory to Troubleshooting
In this session, you’ll learn:
-
The scientific basis and core principles of fiber photometry
-
What fiber photometry can—and can’t—reliably measure
-
How to select the right biosensors for your experimental goals
-
Key design considerations, including controls and signal interpretation
-
Common pitfalls and troubleshooting tips
Key Relationships:
-
Length vs. Loss: More length means more scattering and absorption within the fiber, leading to exponentially reduced light intensity (e.g., a 0.2 dB/m fiber loses 0.2 dB per meter).
-
Loss vs. Signal: Higher light loss means fewer photons reach the detector, resulting in a weaker fluorescence signal and potentially poor signal-to-noise ratio (ΔF/F).
-
Fiber Type (NA/Diameter): Higher Numerical Aperture (NA) or larger core diameters (like 200µm) collect more light and have larger sampling volumes but can also introduce more background noise compared to smaller fibers (like 50µm).
2026-01-13 🌐 🎬 💾 📚 📑
BIO Software define IO (from Xous)
Fused Fiber Photometry
pyPhotometry
Open source, Python based, fiber photometry data acquisition.
PMT vs SiPM
Wireless Fiber Photometry
Creative Thinking Field Guide
2026-003
2026-01-12 🌐 🎬 💾 📚 📑
History is a Process
SiPM AD5934 as Lcok-In Amp
📚Silicon Photomultiplier-based Low-light in vivo Fiber Photometry
AD5934
📚SiPM-based Fiber Photometry and EIS for Cortisol Detection
Lock-in amplifiers AD630
AD75019 16x16 Crosspoint Switch Array
- 256 Switches in a 16 x 16 Array
- Wide Signal Range: to Supply Rails of 24 V or ±12 V
- Low On-Resistance: 200 Ω Typ
- TTL/CMOS/Microprocessor-Compatible Control Lines
- Serial Input Simplifies Interface
Japanese scientists just built human brain circuits in the lab
🌐Japanese scientists just built human brain circuits in the lab
2026-01-09 🌐 🎬 💾 📚 📑
RHD2216-recording-system
WiFi Headstage
WiFi Headstage Currently working on the development of a WiFi headstage designed to study neural activity in awake monkey subjects. This innovative device is intended to replace the existing wired systems with a low-power, permanently installed headstage that captures single-neuron spike activity and provides closed-loop stimulation. The project aims to develop a comprehensive IoT system, integrating everything from the headstage that collects data to the server that stores it for advanced AI analysis. Future enhancements include adding EMG signal acquisition, which will further broaden the scope of research possibilities and applications. Ultimately, this project seeks to revolutionize the field of neural research by providing a more efficient, versatile, and less invasive means of data collection and analysis. Additionally, collaborating with CERVO on projects like the Smart Vivarium, which automates the study of behaviors in groups of mice, enhances the data processing for faster analysis and efficient storage in a database.
Xous Operating System
OV6948 World smallest CCD
LAN866X 10BASE-T1S Endpoints for Smarter Remote Connectivity
2026-01-08 🌐 🎬 💾 📚 📑
Amazon CTO Say in 5 Years (2030) RSA/DES will fail. Because of Quantum Computing
Well, I don't think so.
忽然知道 台灣有事 日本有事的意思了 原來台灣已經託管給日本了 美洲國要退出全球戰略了
2026-01-07 🌐 🎬 💾 📚 📑
OSS CAD Suite
OSS CAD Suite is a binary software distribution for a number of open source software used in digital logic design. You will find tools for RTL synthesis, formal hardware verification, place & route, FPGA programming, and testing with support for HDLs like Verilog, Migen, and Amaranth.
God grant me the serenity to accept the thing
God grant me the serenity to accept the things I cannot change, courage to change the things I can, and wisdom to know the difference.
Reinhold Neibuhr
Kluge The Haphazard Construction of the Human Mind
2026-002
Power Control Chips from AD2
Digilent Analog Discovery 2 Schematics
🌐Digilent Analog Discovery 2 Schematics
ADM1270
The ADM1270 is a current-limiting controller that provides inrush current limiting and overcurrent protection for modular or battery-powered systems. When circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. These transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system.
The ADM1270 is designed to control the inrush current, when powering on the system, via an external P-channel field effect transistor (FET).
To protect the system from a reverse polarity input supply, there is a provision made to control an additional external P-channel FET. This feature prevents reverse current flow in case of a reverse polarity connection, which can damage the load or the ADM1270. The ADM1270 is available in a 3 mm × 3 mm, 16-lead LFCSP and a 16-lead QSOP.
ADP197
Logic Controlled High-Side Power Switch 5V, 3A
ADM1177
The ADM1177 is an integrated hot swap controller that offers digital current and voltage monitoring via an on-chip, 12-bit analog-to-digital converter (ADC), communicated through an I2C interface.
An internal current sense amplifier senses voltage across the sense resistor in the power path via the VCC pin and the SENSE pin.
The ADM1177 limits the current through this resistor by control-ling the gate voltage of an external N-channel FET in the power path, via the GATE pin. The sense voltage (and, therefore, the inrush current) is kept below a preset maximum.
ADCMP671 voltage monitor
The ADCMP671 voltage monitor consists of two low power, high accuracy comparators and reference circuits. It operates on a supply voltage from 1.7 V to 5.5 V and draws only 8.55 μA maximum, making it suitable for low power system monitoring and portable applications. The part is designed to monitor and report supply undervoltage and overvoltage fault.
The past is never dead, It's not even pass
Can Language Models Replace Compilers?
🌐Can Language Models Replace Compilers?
2026-01-06 🌐 🎬 💾 📚 📑
OpenNIC (QDMA)
💾OpenNIC Shell is the Verilog Part
A Good QDMA design Reference for now.
QDMA
2026-01-05 🌐 🎬 💾 📚 📑
Camera for Monochrome >=60fps Global Shulter
OV9281 1/4inch
MT9V032 1/3inch (Obsolete)
MT9V022/24/34
Python480 1/3.5inch
Memory
Your memory is a monster; you forget-it doesn't. It simply files things away. It keeps things for you, or hides things from you-and summons them to your recall with a will of its own. You think you have a memory; but it has you!
-JOHN IRVING
2026-01-02 🌐 🎬 💾 📚 📑
QDMA
📚EXTENSION AND IMPROVEMENT OF A PCIE-BASED FPGA ENVIRONMENT FOR TESTINGHPC ARCHITECTURES
QDMA is designed to move data between devices and memory by using a queue-based approach, an idea derived from the RDMA concept queue set. The main mechanism to perform transfers is through descriptors provided by the host OS. The data can be moved in the H2C direction (write) and the C2H direction (read).
QDMA
📚In-Network Memory Access: Bridging SmartNIC and Host Memory
4.1.2QDMA Queue based Direct Memory Access subsystem (QDMA) is a PCIe-based DMA engine that is optimized for high-bandwidth and high packet count data transfers. As discussed earlier, the mechanism of XDMA uses the descriptors (instructions) provided by the host operating system to transfer data in either direction to and from the device. The QDMA uses queues, derived from queue set concepts of RDMA[55]. The DMA descriptors used for transfers are loaded with the queues, which are assigned as resources to PCIe Physical Functions (PFs) and Virtual Functions (VFs) by the IP. The subsystem is used with an AMD-provided reference driver. It supports both AXI4 and AXI4-Lite interfaces.
The QDMA IP maps external memory into register-mapped space, allowing the FPGA to access memory as if it were a register array, using Base Address Registers (BARS). These BARS are a set of registers in the IP that hold addresses of memory regions that the QDMA IP needs to access. The QDMA IP uses the AXI memory-mapped interface AXI-MM to map the external memory or any instantiated memory, into a register-mapped space. The QDMA drivers on the host pick recognize these BARS from the design when it is correctly configured, allowing us to do DMA transactions over PCIe to access AXI-MM peripherals from the host system.
QDMA differs from XDMA primarily in its queue based architecture, which is designed to support higher packet counts and manage complex data flows more efficiently. While XDMA uses a traditional descriptor based approach to manage data transfers, QDMA implements a queue based system that allows dynamic handling of multiple data streams. This queue based system is derived from RDMA principles and enables QDMA to manage data transfers through dedicated queues, which can be assigned to both PFs and VFs. While XDMA’s simpler, descriptor based model is typically used for straightforward data transfers using Physical channels. In both IPs, the use of AXI4 and AXI4-Lite interfaces allows for compatibility with AXI peripherals.
Learning is
Copy, Mimic
From Mistake
From no where
PCIE to 2.5G-Ethernet
PCIE to USB3 to 2.5G Ethernet
PCIE <-> VL805 <-> RTL8156