2026-01
2026-01-07
OSS CAD Suite
OSS CAD Suite is a binary software distribution for a number of open source software used in digital logic design. You will find tools for RTL synthesis, formal hardware verification, place & route, FPGA programming, and testing with support for HDLs like Verilog, Migen, and Amaranth.
God grant me the serenity to accept the thing
God grant me the serenity to accept the things I cannot change, courage to change the things I can, and wisdom to know the difference.
Reinhold Neibuhr
Kluge The Haphazard Construction of the Human Mind
2026-002
Power Control Chips from AD2
Digilent Analog Discovery 2 Schematics
Digilent Analog Discovery 2 Schematics
ADM1270
The ADM1270 is a current-limiting controller that provides inrush current limiting and overcurrent protection for modular or battery-powered systems. When circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. These transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system.
The ADM1270 is designed to control the inrush current, when powering on the system, via an external P-channel field effect transistor (FET).
To protect the system from a reverse polarity input supply, there is a provision made to control an additional external P-channel FET. This feature prevents reverse current flow in case of a reverse polarity connection, which can damage the load or the ADM1270. The ADM1270 is available in a 3 mm × 3 mm, 16-lead LFCSP and a 16-lead QSOP.
ADP197
Logic Controlled High-Side Power Switch 5V, 3A
ADM1177
The ADM1177 is an integrated hot swap controller that offers digital current and voltage monitoring via an on-chip, 12-bit analog-to-digital converter (ADC), communicated through an I2C interface.
An internal current sense amplifier senses voltage across the sense resistor in the power path via the VCC pin and the SENSE pin.
The ADM1177 limits the current through this resistor by control-ling the gate voltage of an external N-channel FET in the power path, via the GATE pin. The sense voltage (and, therefore, the inrush current) is kept below a preset maximum.
ADCMP671 voltage monitor
The ADCMP671 voltage monitor consists of two low power, high accuracy comparators and reference circuits. It operates on a supply voltage from 1.7 V to 5.5 V and draws only 8.55 μA maximum, making it suitable for low power system monitoring and portable applications. The part is designed to monitor and report supply undervoltage and overvoltage fault.
The past is never dead, It's not even pass
Can Language Models Replace Compilers?
Can Language Models Replace Compilers?
2026-01-06
OpenNIC (QDMA)
OpenNIC Shell is the Verilog Part
A Good QDMA design Reference for now.
QDMA
2026-01-05
Camera for Monochrome >=60fps Global Shulter
OV9281 1/4inch
MT9V032 1/3inch (Obsolete)
MT9V022/24/34
Python480 1/3.5inch
Memory
Your memory is a monster; you forget-it doesn't. It simply files things away. It keeps things for you, or hides things from you-and summons them to your recall with a will of its own. You think you have a memory; but it has you!
-JOHN IRVING
2026-01-02
QDMA
EXTENSION AND IMPROVEMENT OF A PCIE-BASED FPGA ENVIRONMENT FOR TESTINGHPC ARCHITECTURES
QDMA is designed to move data between devices and memory by using a queue-based approach, an idea derived from the RDMA concept queue set. The main mechanism to perform transfers is through descriptors provided by the host OS. The data can be moved in the H2C direction (write) and the C2H direction (read).
QDMA
In-Network Memory Access: Bridging SmartNIC and Host Memory
4.1.2QDMA Queue based Direct Memory Access subsystem (QDMA) is a PCIe-based DMA engine that is optimized for high-bandwidth and high packet count data transfers. As discussed earlier, the mechanism of XDMA uses the descriptors (instructions) provided by the host operating system to transfer data in either direction to and from the device. The QDMA uses queues, derived from queue set concepts of RDMA[55]. The DMA descriptors used for transfers are loaded with the queues, which are assigned as resources to PCIe Physical Functions (PFs) and Virtual Functions (VFs) by the IP. The subsystem is used with an AMD-provided reference driver. It supports both AXI4 and AXI4-Lite interfaces.
The QDMA IP maps external memory into register-mapped space, allowing the FPGA to access memory as if it were a register array, using Base Address Registers (BARS). These BARS are a set of registers in the IP that hold addresses of memory regions that the QDMA IP needs to access. The QDMA IP uses the AXI memory-mapped interface AXI-MM to map the external memory or any instantiated memory, into a register-mapped space. The QDMA drivers on the host pick recognize these BARS from the design when it is correctly configured, allowing us to do DMA transactions over PCIe to access AXI-MM peripherals from the host system.
QDMA differs from XDMA primarily in its queue based architecture, which is designed to support higher packet counts and manage complex data flows more efficiently. While XDMA uses a traditional descriptor based approach to manage data transfers, QDMA implements a queue based system that allows dynamic handling of multiple data streams. This queue based system is derived from RDMA principles and enables QDMA to manage data transfers through dedicated queues, which can be assigned to both PFs and VFs. While XDMA’s simpler, descriptor based model is typically used for straightforward data transfers using Physical channels. In both IPs, the use of AXI4 and AXI4-Lite interfaces allows for compatibility with AXI peripherals.
Learning is
Copy, Mimic
From Mistake
From no where
PCIE to 2.5G-Ethernet
PCIE to USB3 to 2.5G Ethernet
PCIE <-> VL805 <-> RTL8156