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Litex MIPI CSI

ICEStorm Install icestorm_install.md

getting-started-with-litex

Migen Simulation

Counter

from migen import *

class DPLL(Module):
    def __init__(self):
        self.count = Signal(4)

        self.sync += self.count.eq(self.count + 1)

def dpll_test(dut):
    for i in range(20):
         print((yield dut.count))
         yield

if __name__ == "__main__":
    dut = DPLL()
    run_simulation(dut, dpll_test(dut), vcd_name="dpll.vcd")

Migen Selection of Signal from Signal as Index

        shiftout = Array({} for i in range(REG_Number))

        for i in range(16):
            shiftout[0][i] = [self.spi_miso1.eq(Regsiters[0][i] & ~self.spi_cs)]
            shiftout[1][i] = [self.spi_miso2.eq(Regsiters[1][i] & ~self.spi_cs)]

        for i in range(REG_Number):
            self.comb += [
                Case(shift_count, shiftout[i])
            ]

Migen Case

        self.comb += Case(word_cound,{
            0: self.uart_tx.eq(start_b0),
            1: self.uart_tx.eq(start_b1),
            2: self.uart_tx.eq(timestamp_b0),
            3: self.uart_tx.eq(timestamp_b1),
            4: self.uart_tx.eq(timestamp_b2),
            5: self.uart_tx.eq(timestamp_b3),
            "default": self.uart_tx.eq(0),
        })

Migen Module

        encoder = Encoder8b10b()
        decoder = Decoder8b10b()

        self.submodules += [
            encoder, decoder
        ]

Migen Reset FSM

        fsm   = FSM(reset_state="WAIT")
        fsm   = ClockDomainsRenamer("icap")(fsm)
        fsm   = ResetInserter()(fsm)
        self.submodules += fsm
        self.comb += fsm.reset.eq(~(self.write | self.read))

IceStorm toolset for ICE40 FPGA

# Project setup
PROJ      = blinky
BUILD     = ./build
DEVICE    = 8k
FOOTPRINT = ct256

# Files
FILES = top.v

.PHONY: all clean burn timing

all $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin:
    # if build folder doesn't exist, create it
    mkdir -p $(BUILD)
    # synthesize using Yosys
    yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif -json $(BUILD)/$(PROJ).json" $(FILES)
    # Place and route using arachne
    #arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif
    nextpnr-ice40 --hx$(DEVICE) --json build/$(PROJ).json --pcf pinmap.pcf --asc build/$(PROJ).asc
    # Convert to bitstream using IcePack
    icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin

burn: $(BUILD)/$(PROJ).bin
    iceprog $(BUILD)/$(PROJ).bin

timing: $(BUILD)/$(PROJ).asc
    icetime -tmd hx$(DEVICE) $(BUILD)/$(PROJ).asc

clean:
    rm build/*

Chisel FPGA開発日記

https://msyksphinz.hatenablog.com/

https://www.hatena.ne.jp/

https://hatenablog.com/

Agile Hardware Design Video 2024

Chip Alliance

Chip Alliance

Amaranth

Amaranth HDL Document

Verilog

https://verilogguide.readthedocs.io/en/latest/

https://www.chipverify.com/

Verilog Tutorial

The Art of FPGA Design - element14 Community

The Art of FPGA Design - element14 Community

Digital Signal Processing, from Algorithm to FPGA Bitstream - element14 Community

Digital Signal Processing, from Algorithm to FPGA Bitstream

Xilinx Petalinux

使用Buildroot编译AMD/Xilinx Zynq ZC702 单板 Linux （内核和文件系统）

🌐使用Buildroot编译AMD/Xilinx Zynq ZC702 单板 Linux （内核和文件系统）

ZCU104_MPSoC Development - Petalinux 2024.2 Basic Tutorial

🌐ZCU104_MPSoC Development - Petalinux 2024.2 Basic Tutorial

Xillinux

🌐Xillinux: A Linux distribution for Z-Turn Lite, Zedboard, ZyBo and MicroZed

The Xillinux distribution is a software + FPGA code kit for running a full-blown graphical desktop on the Z-Turn Lite, Zedboard and (non-Z7) ZyBo, attaching a monitor, keyboard and mouse to the board itself. Xillinux also supports MicroZed without the graphics.

UltraZed-EG PCIe Carrier Card 開發紀錄

🌐UltraZed-EG PCIe Carrier Card 開發紀錄 使用 PetaLinux 建立系統

Petalinux Demo

🎬Xilinx Zynq & PetaLinux Project Demo

🎬PetaLinux SPI Device Control LCD Panel

🎬Creating Multi-Boot Bitstream In Xilinx FPGA

🎬Xilinx HLS Project Demo - SHA256 Calculation

Perfecting PetaLinux Workshop

💾Perfecting PetaLinux Workshop

🎬Perfecting PetaLinux Workshop

📚PetaLinux Tools Documentation: Reference Guide (UG1144)

Vivado Vitis Petalinux 2024 on Ubuntu 2024

🌐Vivado Vitis Petalinux 2024.2

🌐Hardware acceleration in FPGA with Vivado and Vitis

🌐Vivado 2024 on Ubuntu 2024

Zynq PetaLinux and Vitis

🌐Zynq PetaLinux 2024-1

🌐Fixed Platform Design on Zynq-7000 in Vitis 2024.1

Linux and Programming

Linux Thread

Linuxとpthreadsによる マルチスレッドプログラミング入門｜サポート｜秀和システム Book Link

Linux Kernel Module Programming Guide

https://sysprog21.github.io/lkmpg/

Tutorial 1 https://linux-kernel-labs.github.io/refs/heads/master/#

SSH Turnnel

ssh -f -N -L 127.0.0.1:8888:127.0.0.1:8888 -i pemKey  user@ipaddress
For Jupyter notebook

Chromebook

Install Desktop GUI in chromebook chromebookDesktop.md

DSP

Wavelet

Wavelet_101

Neuro Science

Neuroscience exploration Video

Topological Data Analysis (TDA)

VSCode

VSCode and Docker

LTSpice Tutorial

LTspice Tutorial

LTSpice Tutorial