2026-06
2026-06-04 Thuesday 🌐 🎬 💾 📚 📑 🔬
1M > 1G
2026-06-03 Wednesday 🌐 🎬 💾 📚 📑 🔬
理論極限：不可能的三位一體
根據經濟學原理，一個國家不可能同時實現以下三個目標：
- 資金自由流動（Capital Mobility）
- 獨立的貨幣政策（Monetary Autonomy，如自行決定低利率）
- 穩定的匯率（Exchange Rate Stability）
台灣作為高度依賴外貿的開放經濟體，無法鎖國、必須維持資金自由流動。當央行想要同時把持「低利率」以照顧本土產業，又想「調控匯率」來保護出口商時，實質上是在挑戰這個三角極限。這導致台灣的貨幣政策自主性在國際熱錢（尤其是 AI 科技大舉外銷引發的熱錢）來襲時會逐漸遭到侵蝕。
政策帶來的內部代價
房價長期飆升長期低利率環境提供市場廉價的資金成本，導致大量資金湧入房地產，成為推高全台房價、加劇年輕人購屋負擔的元兇之一。
實質購買力受損當新台幣匯率因政策考量偏低時，會提高能源、糧食及進口原材料的成本（輸入性通膨），實質上削弱了台灣民眾的購買力。
財富分配不均此模式顯著補貼了大型電子出口製造業（如半導體群聚），卻犧牲了廣大需要穩定購買力、面對輸入性通膨的內需傳統產業與一般受薪階級（實質薪資成長停滯）。殭屍企業存款化過低的借貸成本讓缺乏競爭力的邊際企業得以存活，阻礙了產業結構的自然淘汰與升級。
Neuropixels Opto: combining high-resolution electrophysiology and optogenetics
📑Neuropixels Opto: combining high-resolution electrophysiology and optogenetics
Honeybees teach drones how to navigate
🌐Honeybees teach drones how to navigate
💾Efficient robot navigation inspired by honeybee learning flights
2026-06-02 Tuesday 🌐 🎬 💾 📚 📑 🔬
China has approved the world’s first invasive brain-computer chip—here’s what’s next
🌐China first invasive brain-computer chip
NEO beat several other BCIs to approval, including one from Neuralink, a California-based company founded by Elon Musk. Since October 2023, Neuracle has conducted 36 clinical trials using NEO, including the one on Dong. Thirty-two of them took place in the space of a few months in 2025, with the details about one of the four first in-person trials published in a preprint paper last July.
One reason for NEO’s fast approval could be that it has a “relatively less invasive” design than counterparts such as Neuralink’s N1 brain chip, says Avinash Singh, a BCI researcher at the University of Technology Sydney. NEO’s eight sensors sit on top of the brain’s protective membrane while Neuralink’s N1 chip directly penetrates the cortex, the outermost layer of the brain itself. Neuracle’s device faces fewer regulatory constraints because it presents a lower risk of hemorrhage, glial scarring, and long-term signal degradation, Singh says.
Michael Levin Lab
Embodied Minds: understanding diverse intelligence in evolved, designed, and hybrid complex systems
Package Size Compare
The STM32G031 microcontroller is available in several compact packages, ranging from 8 to 48 pins. Physical package dimensions include:
- WLCSP18: (1.86 2.14mm)
- SO8N (SOIC-8): (4.9 6.0 mm)
- UFQFPN20: (3.0 3.0mm) (found in the related STM32C0 series footprint)
- TSSOP20: (6.4 4.4mm)
- UFQFPN28: (4.0 4.0mm)
- LQFP32 / UFQFPN32: (7.0 7.0mm) /(5.0 5.0mm)
- UFQFPN48 / LQFP48: (7.0 7.0mm)
2026-06-01 Monday 🌐 🎬 💾 📚 📑 🔬
On-Line FPAA Workshop
🎬Professor Jennifer Hasler's Circuit Lectures
🌐Analog Neuromorphics: Tools and Techniques
Our goal is to build an analog neuromorphic hardware community fully immersed in developing the tools and infrastructure needed to develop mature analog neuromorphic systems.
FPAA device development has been tightly linked with education of users not involved in that original FPAA design. The ICE (Integrated Computational Electronics) Laboratory from Georgia Tech (GT) developed and evolved a number of FPAA workshops. The initial concepts for these workshops started from educational approaches at GT in analog and neurmorphic circuits, where many of thes approaches build upon the Analog VLSI and Neural Systems (CNS 182) course at Caltech. The first dedicated FPAA workshop session was held at USC in May 2008. Since 2008 this group has averaged one to two workshops a year. As of August 2019, hundreds of individuals have participated in an FPAA workshop in some form.