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2026-08

2026-08-31 Monday 🌐 🎬 💾 📚 📑 🔬

MIPI Pi Dummy Driver

💾Reference to VEYE Driver Install

Source code and dts

💾Dummy Senosor Source Code

💾Dummy Sensor Update Files

🌐Receive FPGA MIPI CSI2 Tx data on Raspberry PI Dummy Sensor

Lattice SOC FPGA Propel 2026.1 Create use Template Issue

export SETUPTOOLS_USE_DISTUTILS=stdlib

The Fractalist

2026-047

迷幻蘑菇

2026-046

輪到你了

2026-045

2026-08-28 Friday 🌐 🎬 💾 📚 📑 🔬

開始使用護膝

最近聽了一個叫 潘若迪 的運動教練 他都全天用護膝 所以我也決定開始學習 不是因為關節有什麽問題 畢竟等有問題了 就都太晚了

🌐有氧天王潘若迪長期穿長褲 主要在掩飾腳上的護膝及鐵條

🎬有氧天王潘若迪長期穿長褲 護膝+長褲顧膝關節

Verilog I2C Master and Slave

💾Verilog I2C

MP5424grm FPGA Power Source

🌐MP5424grm FPGA Power Source

Creating LiteX wrappers

📑Creating LiteX wrappers

CSI-2 Image Simulator Lattice CrosslinkFPGA to Jetson Nano

💾CSI-2 Image Simulator Lattice CrosslinkFPGA to Jetson Nano

🌐CSI-2 Image Simulator Lattice CrosslinkFPGA to Jetson Nano

2026-08-27 Thursday 🌐 🎬 💾 📚 📑 🔬

Use CH347 for OpenFPGALoader

CH347 Support 1.8V 2.5V 3.3V

sudo nano /etc/udev/rules.d/99-ch347.rules

SUBSYSTEM=="usb", ATTRS{idVendor}=="1a86", ATTRS{idProduct}=="55dd", MODE="0666"
SUBSYSTEM=="usb", ATTRS{idVendor}=="1a86", ATTRS{idProduct}=="55de", MODE="0666"

sudo udevadm control --reload-rules
sudo udevadm trigger

China FPGA (CrossLink-NX) Engineer

2026-08-26 Wednesday 🌐 🎬 💾 📚 📑 🔬

2026-08-25 Tuesday 🌐 🎬 💾 📚 📑 🔬

Lattice Semiconductor CrossLink-NX Notes

2026-08-24 Monday 🌐 🎬 💾 📚 📑 🔬

TCP interface to FTDI FT245 synchronous FIFO

💾TCP interface to FTDI FT245 synchronous FIFO

2026-08-21 Friday 🌐 🎬 💾 📚 📑 🔬

2026-08-20 Thuresday 🌐 🎬 💾 📚 📑 🔬

The SYZYGY Hub of Opal Kelly

The SYZYGY Hub

Lattice FPGA, Radiant IDE Document from JP

🎬Radiant IDE Video

🎬Lattice Radiant Archive Seminar

📑Lattice FPGA Design Tool Radiant Japanese Manual

📑Lattice FPGAs on a board, JTAG-related design

📑MIPI standard - For those who want to know about MIPI DSI/CSI!

📑MIPI reference designs

2026-08-19 Wednesday 🌐 🎬 💾 📚 📑 🔬

2026-08-18 Tuesday 🌐 🎬 💾 📚 📑 🔬

無敵合作

2026-044

The Reverse Centaur's Guide to Life after AI

2026-043

上古卷軸4 遺忘之都 NS2 沒有繁體中文

2026-08-17 Monday 🌐 🎬 💾 📚 📑 🔬

2026-08-14 Friday 🌐 🎬 💾 📚 📑 🔬

Receive FPGA MIPI CSI2 Tx data on Raspberry PI No I2C

Receive FPGA MIPI CSI2 Tx data on Raspberry PI

Custom MIPI CSI camera not detected

Dummy CSI

MIPI_CSI2_TX with I2C on Xilinx

MIPI_CSI2_TX with I2C on Xilinx

VHDL code for using LVDS lines of Xilinx FPGA for MIPI CSI-2 TX protocol. The goal is to support sending video or any other data using FPGA that don't have a dedicated D-PHY compatible outputs. (HS and LP outputs modes). The rate is 800Mbit/Sec per lane, two lanes total + DDR clock. The code was tested and works as expected on KC705 evaluation board.

2026-08-13 Thursday 🌐 🎬 💾 📚 📑 🔬

2026-08-12 Wednesday 🌐 🎬 💾 📚 📑 🔬

MIPI FPGA design use Litex on Lattice

SDI to MIPI CSI-2 Video Converter FPGA design (Lattice)

Litex Nexus MIPI

2026-08-11 Tuesday 🌐 🎬 💾 📚 📑 🔬

Litex and Efinix 2026-08

  • Use Ubuntu 22.04 Python > 3.9
  • No venv needed
  • Install Litex along side efinix Tools
  • Pay attention to which python3 path
  • Only set LITEX_ENV_EFINITY="~/efinity-yyyy-d-linux-x64/efinity/yyyy.mm"

2026-08-10 Monday 🌐 🎬 💾 📚 📑 🔬

我看到的世界跟你不一樣

2026-042

ㄜ 都是正面溫馨 讓人覺得像迪士尼樂園

Skin in the Game

2026-041

Incerto 系列 除了語錄外 又看完一遍了 這套書是我 這輩子少數 會一讀再讀的書

2026-08-07 Friday 🌐 🎬 💾 📚 📑 🔬

💾LiteX MIPI CSI testing on CrossLink NX VIP

Efinix Mipi as Data Channel to ARM

💾Efinix Mipi as Data Channel to ARM

💾RAH Protocol User Guide

💾FIXED-POINT TO FLOATING-POINT & FLOATING-POINT TO FIXED-POINT CONVERSION

💾MIPI_CSI_T20F169

2026-08-06 Thursday 🌐 🎬 💾 📚 📑 🔬

2026-08-05 Wednesday 🌐 🎬 💾 📚 📑 🔬

Librelane ASIC EDA Tools Flow Integration

LibreLane

LibreLane is a powerful and versatile infrastructure library that enables the construction of digital implementation flows for application specific integrated circuits (ASICs) based on open-source and commercial electronic design automation (EDA) tools.

📑Librelane Get Start

Open Source Serdes

💾OpenSERDES

Technology: Skywater OpenPDK 130nm

Tools Used: OpenLane, Virtuoso Cadence

The Serializer and Deserializer blocks are coded in Verilog HDL and synthesized using Openlane tool mapped to Sky130 CMOS technology. Simulation results and associated gds, spice and netlist files are uploaded in Serializer and Deserializer folders respectively

How to turn every FPGA LVDS pair into a complete SERDES solution

🌐How to turn every FPGA LVDS pair into a complete SERDES solution

2026-08-04 Tuesday 🌐 🎬 💾 📚 📑 🔬

DearPyGUI for Labview Like GUI

🌐DearPyGUI

FPGA vs SoC: How They Differ and Which One to Choose

🌐FPGA vs SoC via Digilent

2026-08-03 Monday 🌐 🎬 💾 📚 📑 🔬

PICO ICE

PICO ICE

PICO + ICE40-5K FPGA

Maybe One Day We Will Ban LLM Usage ? In 5 Years.

PhAT GUI

pyPhotometry Hardware and Software

用界線讓孩子放下手機

2026-040

Antifragile

2026-039