2026-08
2026-08-05 Wednesday 🌐 🎬 💾 📚 📑 🔬
Librelane ASIC EDA Tools Flow Integration
LibreLane is a powerful and versatile infrastructure library that enables the construction of digital implementation flows for application specific integrated circuits (ASICs) based on open-source and commercial electronic design automation (EDA) tools.
Open Source Serdes
Technology: Skywater OpenPDK 130nm
Tools Used: OpenLane, Virtuoso Cadence
The Serializer and Deserializer blocks are coded in Verilog HDL and synthesized using Openlane tool mapped to Sky130 CMOS technology. Simulation results and associated gds, spice and netlist files are uploaded in Serializer and Deserializer folders respectively
How to turn every FPGA LVDS pair into a complete SERDES solution
🌐How to turn every FPGA LVDS pair into a complete SERDES solution
2026-08-04 Tuesday 🌐 🎬 💾 📚 📑 🔬
DearPyGUI
FPGA vs SoC: How They Differ and Which One to Choose
2026-08-03 Monday 🌐 🎬 💾 📚 📑 🔬
PICO ICE
PICO + ICE40-5K FPGA
Maybe One Day We Will Ban LLM Usage ? In 5 Years.
Fiber Photometry Related Open Source Tools
pyPhotometry Hardware and Software
用界線讓孩子放下手機
2026-040
Antifragile
2026-039