2026-09

2026-09-11 Friday 🌐 🎬 💾 📚 📑 🔬

2026-09-10 Thursday 🌐 🎬 💾 📚 📑 🔬

正念老化

2026-049

布魯克林有棵樹

2026-048

2026-09-09 Wednesday 🌐 🎬 💾 📚 📑 🔬

Open Source SPI MIPI Bridge with FPGA: Driving IPOD Nano 6 MIPI LCD Using FPGA

🌐Open Source SPI MIPI Bridge with FPGA: Driving IPOD Nano 6 MIPI LCD Using FPGA

💾MIPI Bridge with FPGA

🎬MIPI Bridge with FPGA

Linux CPU Isolation & Low-Latency Processing Guide

CPU isolation involves dedicating specific processor cores exclusively to time-critical workloads while shielding them from operating system noise, scheduler preemption, timer ticks, and hardware interrupts.

1. Purpose of CPU Isolation

In standard Linux configurations, the kernel constantly balances tasks, handles hardware interrupts, and executes timer ticks across all available cores. For hard real-time or high-throughput workloads, this introduces variable kernel noise or jitter. Key benefits of isolation include:

Sub-Microsecond Determinism: Eliminates involuntary preemption and context switches for latency-critical applications such as trading systems, robotics, and industrial control loops.
Cache Locality: Ensures code and data structures remain resident in L1, L2, and L3 processor caches, eliminating memory bus fetch delays.
High-Speed Packet Processing: Prevents ring buffer overflows and packet drops in frameworks like DPDK or VPP that rely on tight polling loops.

2. Kernel Boot Parameters

The foundation of CPU isolation is configured via kernel command-line arguments in GRUB:

isolcpus: Removes designated CPUs from the kernel scheduler's load-balancing domain so general tasks are never automatically scheduled on them.
nohz_full: Enables adaptive-tickless mode, stopping the periodic kernel timer tick on isolated cores as long as only a single userspace task is running.
rcu_nocbs: Offloads Read-Copy Update (RCU) callbacks away from isolated CPUs onto non-isolated housekeeping cores.
irqaffinity: Restricts default hardware interrupt (IRQ) handling to specified housekeeping cores.
intel_pstate=disable / nosmt: Disables dynamic power scaling and Hyper-Threading to prevent hardware preemption and frequency fluctuations.

Example GRUB Configuration

To isolate CPUs 2 and 3 while reserving CPUs 0 and 1 for housekeeping:

GRUB_CMDLINE_LINUX_DEFAULT="quiet splash isolcpus=domain,2,3 nohz_full=2,3 rcu_nocbs=2,3 irqaffinity=0,1 intel_pstate=disable"

3. Interrupt Handling & Steering (IRQ Affinity)

Hardware interrupts must be routed away from isolated cores to prevent latency spikes:

Disabling `irqbalance` on Isolated Cores

To prevent the irqbalance daemon from assigning interrupts to isolated cores, edit /etc/default/irqbalance or /etc/sysconfig/irqbalance:

# Exclude CPUs 2 and 3 using a CPU list or bitmask
IRQBALANCE_BANNED_CPULIST="2,3"
# Or using hexadecimal bitmask (e.g., bits 2 and 3 = 0x0C)
IRQBALANCE_BANNED_CPUS=0000000c

Manual IRQ Steering

Check active interrupts via /proc/interrupts and write hexadecimal CPU masks directly to /proc/irq/<IRQ_NUM>/smp_affinity:

# Direct IRQ 142 to run exclusively on CPU 0 (hex mask 0x1)
echo 1 > /proc/irq/142/smp_affinity

4. Workload Isolation via `systemd` Slices (cgroups v2)

Modern Linux distributions recommend using systemd to manage cgroup resource partitioning rather than calling deprecated legacy utilities.

Step 1: Restrict System and User Workloads to Housekeeping Cores

Restrict OS processes, system daemons, and user sessions to housekeeping CPUs (e.g., CPUs 0–10):

sudo systemctl set-property --runtime init.scope AllowedCPUs=0-10
sudo systemctl set-property --runtime system.slice AllowedCPUs=0-10
sudo systemctl set-property --runtime user.slice AllowedCPUs=0-10

Step 2: Create a Dedicated Real-Time Slice

Create a slice allocated exclusively to isolated CPU 11:

sudo systemctl set-property --runtime custom-workload.slice AllowedCPUs=11

Step 3: Run the Real-Time Application

Launch the application inside a transient scope bound to the isolated slice:

systemd-run --scope -p Slice=custom-workload.slice /usr/local/bin/my_rt_app

5. Application Binding & Low-Latency Design

Programmatic Core Pinning

In C/C++, use sched_setaffinity(2) or pthread_setaffinity_np(3) to bind execution threads directly to isolated cores:

#define _GNU_SOURCE
#include <sched.h>
#include <stdio.h>

int main() {
    cpu_set_t cpuset;
    CPU_ZERO(&cpuset);
    CPU_SET(11, &cpuset); // Target isolated CPU core 11

    if (sched_setaffinity(0, sizeof(cpu_set_t), &cpuset) == -1) {
        perror("sched_setaffinity failed");
        return 1;
    }
    // Application core loop executes here on CPU 11...
    return 0;
}

Command-Line Pinning via `taskset`

Run executables with a specific CPU mask or list using taskset(1):

# Launch a process pinned strictly to CPU 3
taskset -c 3 /usr/local/bin/my_app

# Pin an existing PID to CPU 0
taskset -p 0x1 <PID>

Low-Latency Software Guidelines ("Bare Metal Mode")

Poll-Mode Loops: Use tight polling loops instead of yielding or sleeping to avoid triggering scheduler preemption.
Lock Physical Memory: Call mlockall(MCL_CURRENT | MCL_FUTURE) at program launch to prevent swapping and page faults.
Avoid System Calls in Fast Paths: System calls (syscalls) switch execution into the kernel, introducing synchronous noise, memory barriers, and RCU tracking penalties.
Offload Logging: Write logging data to a lock-free ring buffer in userspace and let a separate helper thread on a housekeeping core perform console or file I/O.

美軍攻擊油輪的方式不會造成波撕灣的生態問題嘛？還是美國人要搞爛中東一切

2026-09-08 Tuesday 🌐 🎬 💾 📚 📑 🔬

PyUSB

💾PyUSB

PyUSB provides for easy access to the host machine's Universal Serial Bus (USB) system for Python 3.

MicroMAP: Low cost, high performance package for electrophysiological recording

📚MicroMAP Paper

Objective: To develop an accessible, low-cost, and open-source system for multi-channel electrophysiological recordings across multiple brain regions, facilitating the investigation of neural dynamics and information flow in long-range integration.
Approach: We designed a digital signal acquisition system that integrates two programmable analog-to-digital converter chipsets – Intan RHD and Texas Instruments ADS – with an Arduino-based microcontroller. In addition, we introduce a custom-designed headstage and a methodology for spatially distributed electrode placement using a perforated printed circuit board, which interfaces directly with the system to enable local field potential recordings from multiple brain regions. The system successfully recorded biopotentials without significant sample loss and performed comparably to gold-standard systems, enabling recordings across 32 channels at a 2 kHz sampling frequency. We verified signal integrity and stability under both experimental and simulated conditions, confirming the platform’s suitability for electrophysiology.
Main results: We present a comprehensive, low-cost bioengineering solution for distributed electrophysiological recordings, enabling detailed investigation of brain dynamics through synchronized neural activity across regions.
Significance: This open-source platform enables neuroscience laboratories to investigate large-scale neural interactions with high temporal precision, expanding access to systems neuroscience tools essential for understanding interregional brain connectivity.

2026-09-07 Monday 🌐 🎬 💾 📚 📑 🔬

Dimensionality—neuroscience’s red herring?

🌐Dimensionality—neuroscience’s red herring?

Placing too much emphasis on a specific interpretation of dimensionality, or treating it as an end-all quantification of some aspect of neural computation, may hinder progress in understanding the brain.

Data Center Terrorist

我曾經做過一個回到未來的夢 (2010年做的夢) 
裡面有關 21世紀發生的 Data Center Terrorist 事件
造成Google Amazon 這些公司的衰微
看到現在因為 LLM NTP (Next Token Predictor) <-- 我才不會稱那些叫AI
大規模的建設資料中心 而遭到人民出來抗爭
忽然覺得 Data Center Terrorist 好像不是那麽的 不可思議

2026-09-04 Friday 🌐 🎬 💾 📚 📑 🔬

CH32 RISC-V User Group

📑CH32 RISC-V User Group

Meta harness makes 10 times better Kimi K3 chip

🌐Meta harness makes 10 times better Kimi K3 chip

CH32H417 Examples on Github

💾Rovari SDK

WCH ships an EVT (a vendor HAL) for every chip. It works, and the heavy stacks in it are the only implementations that exist for USB, Ethernet, and the other complex peripherals. It is also inconsistent between peripherals, thinly documented in English, and unpleasant to read.

The Rovari SDK is a clean layer on top of the EVT, not a replacement for it. You get a coherent API across chips, and the vendor stacks stay reachable underneath whenever you need them. The idea is not to support every chip, but the idea behind the project is that the ones it does support should be easy to use. It's intended for people new to the RISC-V ecosystem who are accustomed to something like an Arduino or Raspberry Pi Pico but want a bit more power to explore while having a comfortable layer to fall back on. Currently the targets are WCH RISC-V chips and Baochip-1x RISC-V targets.

Rovari is really simple to use and provides an abstract layer that's easy to peel back if you need to.

💾16通道200MHz逻辑分析仪

💾OpenSourceLogic-CH32H417

💾CH32H417Q_DevBrd

FTDI 245 FIFO Tutorial with Visual Studio and a Lattice MachXO2 FPGA

This guide explains how to use the FTDI D2XX driver and library to transfer data via the "FTDI Synchronous 245 FIFO" protocol. I used a PC running Visual Studio 2019 to communicate with a Lattice MachXO2 FPGA. 1GB of data was transferred at a speed of approximately 355Mbps.

I start by showing how to find all of the relevant documentation for the FTDI UM232H development board and the D2XX API. I show example Verilog code for the Lattice MachXO2 FPGA and explain how it works. Then I show how to configure a Visual Studio 2019 project and write the demo software. Finally, I benchmarked the transfer speed, with a result of 355Mbps.

Source code and links to all of the documentation are available on my web site:

http://www.farrellf.com/projects/software/2020-04-18_FTDI_Sync_245_FIFO_Tutorial__D2XX_with_Visual_Studio_2019/

老人存款最後死的全部拿去一年1萬日幣

人類發明文字來記錄思考

因為大腦的限制人類發明文字來記錄思考因此在這個外循環中讓記錄的思考越來越清晰與正確所以人類會花時間推敲

2026-09-03 Thursday 🌐 🎬 💾 📚 📑 🔬

NASA e-Books

📚NASA e-Books

Read and download free NASA e-Books on the agency’s history, aeronautics research, science missions, and the International Space Station.

FPGA use SX3 Fifo Example

💾FPGA use SX3 Fifo Example

Adiuvo Forgix LiteX Test

💾Adiuvo Forgix LiteX Test

This repository documents one practical test flow for the LiteX-Boards adiuvo_forgix target: build the RP2350 SPIBone design, load the FPGA from MicroPython, then exercise LiteX CSRs over SPIBone.

2026-09-02 Wednesday 🌐 🎬 💾 📚 📑 🔬

CH569-serdes reverse-engineering

💾CH569-serdes reverse-engineering

hydrausb3

How to Configure CPU Isolation for Real-Time Tasks on Ubuntu

sudo tee /usr/local/bin/setup-rt-isolation.sh > /dev/null <<'SCRIPT'
#!/bin/bash
# Set up CPU isolation for real-time tasks
set -e

ISOLATED_CPUS="2,3"
OS_CPUS="0,1"

# Move IRQs off isolated CPUs
for irq_dir in /proc/irq/*/; do
    if [ -w "${irq_dir}smp_affinity_list" ]; then
        echo "$OS_CPUS" > "${irq_dir}smp_affinity_list" 2>/dev/null || true
    fi
done

# Set RCU kthread affinity
for rcu_thread in $(pgrep -f rcu); do
    taskset -cp "$OS_CPUS" "$rcu_thread" 2>/dev/null || true
done

# Move kworker threads off isolated CPUs
for kworker in $(pgrep kworker); do
    taskset -cp "$OS_CPUS" "$kworker" 2>/dev/null || true
done

echo "RT isolation setup complete. Isolated CPUs: $ISOLATED_CPUS"
SCRIPT

sudo chmod +x /usr/local/bin/setup-rt-isolation.sh

# Create a systemd service to run it at boot
sudo tee /etc/systemd/system/rt-isolation.service > /dev/null <<'EOF'
[Unit]
Description=Real-Time CPU Isolation Setup
After=multi-user.target

[Service]
Type=oneshot
ExecStart=/usr/local/bin/setup-rt-isolation.sh
RemainAfterExit=yes

[Install]
WantedBy=multi-user.target
EOF

sudo systemctl daemon-reload
sudo systemctl enable rt-isolation

2026-09-01 Tuesday 🌐 🎬 💾 📚 📑 🔬

Gpio5 For The Pi 5, P500 and CM5

💾GPIO5

The Gpio5 library provides functions to let you work with the GPIO, PWM, I2C and SPI interfaces provided by the RP1 in the Raspberry Pi 5, P500 and CM5.

Raspberry Pi 5 GPIO & libgpiod Reference Guide

Core Summary

libgpiod does not support Direct Memory Access (DMA) on the Raspberry Pi 5. This architecture shift is driven by hardware layout changes introduced in the Pi 5's design.

Technical Comparison: Older Pi Models vs. Raspberry Pi 5

Feature	Older Pi Models (Pi 3, Pi 4)	Raspberry Pi 5
GPIO Controller	Integrated directly into the main Broadcom SoC.	Separated onto the external RP1 Southbridge chip.
Bus Interface	Memory-mapped directly to the system bus.	Connected to the main SoC over a PCIe x1 lane.
High-Speed Control	Direct register manipulation & DMA hacks (`pigpio`).	Strict kernel-space driver control over PCIe.
Interface Library	`/dev/mem` bypasses or kernel drivers.	Standard libgpiod (`/dev/gpiochip*`) interface.

Why libgpiod + DMA Fails on Pi 5

Kernel Abstraction: libgpiod interacts via safe, standard character device system calls. It never interacts with physical hardware addresses directly.
The RP1 Barrier: Physical addresses for GPIO registers no longer reside in the main processor's memory map. They exist on the peripheral side of the PCIe bus.
Legacy Library Breakage: Popular DMA-reliant libraries (like pigpio or rpi_ws281x using direct /dev/mem access) are fundamentally incompatible with the Pi 5's architecture.

High-Speed & Hardware Alternatives

If your project requires high-speed streaming or precision timing that traditionally relied on DMA, use these dedicated hardware subsystems instead:

Hardware PWM: Use the native Linux /sys/class/pwm/ sysfs interface or kernel drivers to offload precision signal generation to the RP1 hardware timers.
SPI / I2C Subsystems: Offload serial data streaming to hardware-backed kernel interfaces (/dev/spidev* and /dev/i2c-*), which handle timing inside the kernel.
RP1 PIO (Programmable I/O): Utilize the RP1 chip's built-in PIO blocks (similar to the RP2040/Raspberry Pi Pico) for custom high-speed digital state machines.

Direct Pi 5 RP1 IO Processor Control Sample

💾rpi5-rp1-gpio

💾rpi5-rp1-spi

CPU Isolation and Task Affinity for Multicore Optimization on Pi

📚CPU Isolation and Task Affinity for Multicore Optimization

Data Plane Development Kit (DPDK)

Data Plane Development Kit (DPDK): For extreme, latency-sensitive workloads like high-bandwidth network processing, applications can utilize DPDK . DPDK bypasses the kernel's networking stack to provide direct userspace access to network hardware . DPDK applications are programmed around a poll-mode model where worker cores run in a tight, uninterrupted loop to continuously drain queue rings .

CH32H417 and CH569 as USB3 Interface

DSCope M454 use CH569 as USB3 Interface

Other USB3 Interface Chip

FT60x
Cypress FX3, SX3
Cypress FX5, FX10, FX20